[Dwarf-Discuss] Register kinds

Relph, Richard Richard.Relph at amd.com
Mon Nov 1 09:42:44 PDT 2010


> Relph, Richard wrote:
> 
> >     This is an abstraction of the capabilities of AMD GPUs. The IL is
> > itself compiled to machine code by a shader compiler (a version of
> which
> > is also used for OpenGL and Direct X.) We’re defining the debug layer
> at
> > the IL stage to support multiple different GPU architectures.
> 
> 
> >     It’s the theoretically unbounded nature of the IL GPRs that is
> > giving me fits at the moment.
> 
> If registers in the IL are subsequently mapped to
> actual hardware registers, these are the ones that
> should be listed in the DWARF data.  How do you
> plan to relate the IL registers to the hardware
> registers?
The debugger itself works at the IL level. It refers to resources it wishes to inspect using their IL 'names'. Registers and memory locations and even 'program counters'.

> DWARF is intended to provide a description of the
> mapping between the source and the executable code
> which runs on the hardware.  If you are planning on
> using DWARF to describe the mapping between source
> and an intermediate language, you are heading off
> into unexplored territory.  I suspect that there are
> many areas where DWARF does not provide sufficient
> information to describe an intermediate language
> which is later translated into machine language.
I appreciate the warning. And I wish we could debug at 'machine level'. But that decision isn't really up for review.
What areas do you think might be particularly problematic?

Thanks,
Richard


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