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<p class="MsoNormal"><span style="color:#80340D">Thanks for the information.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D">There are unofficial patches to both gcc and gdb to support 6809. Neither of them support DWARF.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D">As you said, MAME could in theory just come up with a register mapping, and compiler writers (e.g., CMOC for 6809) would have to adhere to that mapping to be compatible with MAME. And we’d definitely want to
publish that mapping. It would need to be published somewhere obvious and official enough that others would find it--even if MAME is not their target scenario. For example, if gcc or gdb decided to officially support 6809 years later, MAME would be in a
tough spot if they chose a different mapping.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D">Might it be possible for someone to publish register mappings for CPUs without ABIs somewhere on
<a href="https://dwarfstd.org/">https://dwarfstd.org/</a>?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D">Or, are there ways to write custom tags into DWARF to identify it as a "MAME-compatible", so MAME could detect when the register mapping is compatible?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D">Thanks again for your help!<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D">David<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#80340D"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-family:"Calibri",sans-serif;mso-ligatures:none">From:</span></b><span style="font-family:"Calibri",sans-serif;mso-ligatures:none"> John DelSignore <JDelSignore@perforce.com>
<br>
<b>Sent:</b> Monday, May 5, 2025 4:07 AM<br>
<b>To:</b> David Broman <davbrdavbr@hotmail.com>; dwarf-discuss@lists.dwarfstd.org<br>
<b>Cc:</b> John DelSignore <JDelSignore@perforce.com><br>
<b>Subject:</b> RE: DWARF on vintage CPUs<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi David,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">There’s no standard ABI document (that I could find). You might want to look in the GDB sources on the off chance that it supported at some point.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Ultimately, the thing that matters is how the compilers you are using numbers the registers. There is a decent description of the microprocessor here:
<a href="https://en.wikipedia.org/wiki/Motorola_6809">https://en.wikipedia.org/wiki/Motorola_6809</a>, which contains as model of the registers here:
<a href="https://en.wikipedia.org/wiki/File:6809_Internal_Registers.svg">https://en.wikipedia.org/wiki/File:6809_Internal_Registers.svg</a>. It’s up to the compilers, but the numbering of the registers might be something like: D=0, A=1, B=2, X=3, Y=5, U=6,
S=7, PC=8, DP=9, and CC=10. So, for example, when you see register 6 in the DWARF, you’ll know it’s register U. And whatever numbering you pick, you should publish it somewhere so that others can know the register numbering you picked.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Cheers, John D.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b><span style="font-family:"Calibri",sans-serif;mso-ligatures:none">From:</span></b><span style="font-family:"Calibri",sans-serif;mso-ligatures:none"> Dwarf-discuss <<a href="mailto:dwarf-discuss-bounces~jdelsignore=perforce.com@lists.dwarfstd.org">dwarf-discuss-bounces~jdelsignore=perforce.com@lists.dwarfstd.org</a>>
<b>On Behalf Of </b>David Broman via Dwarf-discuss<br>
<b>Sent:</b> Sunday, May 4, 2025 10:36 PM<br>
<b>To:</b> <a href="mailto:dwarf-discuss@lists.dwarfstd.org">dwarf-discuss@lists.dwarfstd.org</a><br>
<b>Subject:</b> [Dwarf-discuss] DWARF on vintage CPUs<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi, all, a question that may be out of scope for this list, but I’m hoping someone here might have answers anyway or be able to point me in the right direction.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I’m considering using DWARF for reading / writing debugging information for Motorola 6809 programs, but the first issue I come to is this from the DWARF 5 spec, where it references the mapping between registers and numbers:<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">“Note that the register number represents a DWARF specific mapping of numbers onto the actual registers of a given architecture… It is recommended that this mapping be defined by the ABI authoring committee for each architecture”<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">In the case of the 6809 I have found no standard register mapping (likely similar situation with other vintage CPUs).<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<ol style="margin-top:0in" start="1" type="1">
<li class="MsoListParagraph" style="margin-left:0in;mso-list:l3 level1 lfo3">Maybe I just missed it… Does anyone know of an official register mapping for 6809?<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l3 level1 lfo3">If not, do you know who I would ask about this, or how a standard register mapping could get defined for 6809?<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l3 level1 lfo3">Can you think of other problems I might encounter later, trying to use DWARF for 6809 or other vintage CPU programs?<o:p></o:p></li></ol>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Background: The MAME project (<a href="https://www.mamedev.org/">https://www.mamedev.org/</a>) emulates many old machines, CPUs, and other hardware. It comes with a built-in disassembly debugger for the currently emulated CPU. I’m working
on adding a feature to the debugger to allow for source-level debugging (useful for developing new software for emulated CPUs). This involves modifying build tools that target emulated machines to output debugging information, and MAME to consume that debugging
information. Largely for assemblers, but also for C-like or BASIC compilers. Features would include:<o:p></o:p></p>
<ul style="margin-top:0in" type="disc">
<li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo6">Source line mapping<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo6">Symbol resolution (where C-like compilers might store variables at offsets to a register, thus requiring the register mapping)<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo6">Maybe at some point in the future: stack unwinding (for compilers).<o:p></o:p></li></ul>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks for your help!<o:p></o:p></p>
<p class="MsoNormal">David<o:p></o:p></p>
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